A conventional structure of a multimedia application, such as a video codec complying with H.264 specification, as shown in FIG. 1, includes a Discrete Cosine Transformation (DCT) operation circuit 110, a Quantization (Q) unit 120, an Inverse Quantization (IQ) unit 130, and an Inverse DCT (IDCT) operation circuit 140. The DCT operation circuit 110 acts in a Row in Column out (R→C) mode, and the IDCT operation circuit 140 also acts in a Row in Column out mode, and receives the output of the IQ unit 130.
In practice, the DCT operation circuit 110 and the IDCT operation circuit 140 must operate complying with a specification, otherwise mismatch between an encoding path and a decoding path will occur, resulting in a “drifting” effect during video playback. However, in some cases, the R→C operation of the IDCT operation circuit 140 is not straightforward in data flow, and a transposition is needed, accordingly. In addition, the prior art needs an extra buffer 135 to store data temporarily, for transforming Column data outputted from the DCT operation circuit 110 into Row data to be inputted to the IDCT operation circuit 140, thereby leading to both increases in processing time and cost of the video codec.
Therefore, an IDCT scheme for processing in a Column in Row out (C→R) mode, capable of real-time compensation, and requiring no extra buffer for temporarily storing data, so as to reduce processing time and cost in a video codec, is needed.